Hydra: an Energy-efficient and Reconfigurable Network Interface

Burgwal van de, M.D. and Smit, G.J.M. and Rauwerda, G.K. and Heysters, P.M. (2006) Hydra: an Energy-efficient and Reconfigurable Network Interface. In: International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2006, 26-29 June 2006, Las Vegas, Nevada, USA.

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Abstract:	In heterogeneous tiled System-on-Chip architectures a Network-on-Chip is used to transport messages between processing elements. A reconfigurable network interface is used to connect the processing elements to the Network-on-Chip, converting the messages between both domains. This paper introduces the Hydra: a network interface for the Montium TP, a coarse-grained reconfigurable processor designed for DSP algorithms. We show that the Hydra is energy-efficient and provides the flexibility required to interface processing elements like the Montium TP.
Item Type:	Conference or Workshop Item
Copyright:	© 2006 CSREA Press
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Computer Architecture for Embedded Systems (CAES)
Link to this item:	http://purl.utwente.nl/publications/62883
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