Hydra: an Energy-efficient and Reconfigurable Network Interface


Burgwal, M.D. van de and Smit, G.J.M. and Rauwerda, G.K. and Heysters, P.M. (2006) Hydra: an Energy-efficient and Reconfigurable Network Interface. In: International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2006, 26-29 June 2006, Las Vegas, Nevada, USA (pp. pp. 171-177).

[img] PDF
Restricted to UT campus only
: Request a copy
Abstract:In heterogeneous tiled System-on-Chip architectures a Network-on-Chip is used to transport messages between processing elements. A reconfigurable network interface is used to connect the processing elements to the Network-on-Chip, converting the messages between both domains. This paper introduces the Hydra: a network interface for the Montium TP, a coarse-grained reconfigurable processor designed for DSP algorithms. We show that the Hydra is energy-efficient and provides the flexibility required to interface processing elements like the Montium TP.
Item Type:Conference or Workshop Item
Copyright:© 2006 CSREA Press
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/62883
Export this item as:BibTeX
HTML Citation
Reference Manager


Repository Staff Only: item control page

Metis ID: 238028