Increasing SoC Dependability via Known Good Tile NoC Testing


Kerkhoff, H.G. and Kuiken, O.J. and Zhang, Xiao (2008) Increasing SoC Dependability via Known Good Tile NoC Testing. In: FastAbs Track of The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN2008), 24-27 June 2009, Anchorage, Alaska.

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Abstract:Advanced CMOS technology possibilities, power, communication and flexibility issues as well as the design gap are directing System-on-Chip (SoC) platforms towards Network-on-Chip (NoC) interconnected identical processing tiles (PT) such as the Montium processor [1]. It is broadly acknowledged that advanced technologies below 45nm come with significant yield and reliability problems, necessitating dependable designs [2]. Our approach for a dependable SoC heavily depends on the regularity within our streaming-data applications SoC. The chip consists of many identical NoC segments and identical PT’s.
Boundary condition is that target applications do not require all available fault-free resources, such as routing segments and PTs.
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Electrical Engineering, Mathematics and Computer Science (EEMCS)
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