Comparison of gate capacitance extraction methodologies

Kazmi, S.N.R. and Schmitz, J. (2008) Comparison of gate capacitance extraction methodologies. In: Proceedings of the 11th annual workshop on semiconductor advances for future electronics and sensors (SAFE 2008), 27-28 Nov 2008, Veldhoven, The Netherlands.

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Abstract:	In recent years, many new capacitance-voltage measurement approaches have been presented in literature. New approaches became necessary with the rapidly increasing gate current density in newer CMOS generations. Here we present a simulation platform using Silvaco software, to describe the full chain from fabrication process until signal interpretation of an NMOS C-V test structure. The platform allows a verification of the validity of an assumed extraction procedure from high-frequency or RF C-V measurements.
Item Type:	Conference or Workshop Item
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Semiconductor Components (SC)
Link to this item:	http://purl.utwente.nl/publications/62607
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Metis ID: 254998