A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection


Ru, Z. and Klumperink, E.A.M. and Nauta, B. (2008) A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection. In: IEEE International Solid-State Circuits Conference, ISSCC 2008, 3-7 February 2008, San Francisco, CA, USA (pp. 322-323+616).

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Abstract:A discrete-time mixing architecture for software-defined radio receivers exploits 8 RF voltage oversampling followed by charge-domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Noise folding is also reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <20mW power consumption including multi-phase clock generation.
Item Type:Conference or Workshop Item
Copyright:© 2008 IEEE
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/62387
Official URL:https://doi.org/10.1109/ISSCC.2008.4523187
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