Advantages of Shift Registers over DLLs for Flexible Low Jitter Multiphase Clock Generation

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Gao, Xiang and Klumperink, Eric A.M. and Nauta, Bram (2008) Advantages of Shift Registers over DLLs for Flexible Low Jitter Multiphase Clock Generation. IEEE Transactions on Circuits and Systems II - Express Briefs, 55 (3). pp. 244-248. ISSN 1549-7747

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Abstract:In this paper, we compare a shift register (SR) to a delay-locked loop (DLL) for flexible multiphase clock generation, and motivate why a SR is not only more flexible but often also better. For a given power budget, we show that a SR almost always generates less jitter than a DLL, assuming both are realized with current-mode logic. This is due to differences in jitter accumulation and the possibility to choose latch delays in a SR much smaller than the delays of DLL elements. For N-phase clock generation, a SR also functions as a divide-by-N and requires a voltage-controlled oscillator with N-times higher frequency. However, this does not necessary lead to more power consumption and can even have advantages like higher Q and less area for the inductors.
Item Type:Article
Copyright:© 2008 IEEE
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/62381
Official URL:http://dx.doi.org/10.1109/TCSII.2008.918972
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Metis ID: 255946