VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture


Gruian, Flavius and Westmijze, Mark (2008) VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture. In: ACM Symposium on Applied Computing, SAC 2008, 16-20 March 2008, Fortaleza, Brazil (pp. pp. 1492-1497).

[img] PDF
Restricted to UT campus only
: Request a copy
Abstract:This paper compares two hardware design flows, based on the classic VHDL on one side and the relatively new Blue-spec System Verilog (BSV) on the other side. The comparison is based on a case study of a Java embedded architecture, comprising a Java native processor and a memory management unit. The processor is a micro-programmed, pipelined, Java-optimized processor (JOP), initially written in VHDL, and its BSV re-designed match BLUEJEP. Its memory management unit implements the bytecodes dealing with memory allocation, along with a mark-compact garbage collector. The two design flows are examined from several points of view, including both quantitative and qualitative measures. Based on this design experience, we conclude that the new high-abstraction level languages, such as BSV, offer in comparison to register-transfer (RT) level classic approaches roughly the same trade-offs that C++ offers vs. assembly language in the software world.
Item Type:Conference or Workshop Item
Copyright:© 2008 ACM
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/62372
Official URL:http://doi.acm.org/10.1145/1363686.1364037
Export this item as:BibTeX
HTML Citation
Reference Manager


Repository Staff Only: item control page

Metis ID: 263686