Revisiting Resistance Speeds Up I/O-Efficient LTL Model Checking


Barnat, J. and Brim, L. and Šimeček, P. and Weber, M. (2008) Revisiting Resistance Speeds Up I/O-Efficient LTL Model Checking. In: 14th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, TACAS 2008, 29 Mar - 06 Apr 2008, Budapest, Hungary (pp. pp. 48-62).

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Abstract:Revisiting resistant graph algorithms are those that can tolerate
re-exploration of edges without yielding incorrect results.
Revisiting resistant I/O efficient graph algorithms exhibit
considerable speed-up in practice in comparison to non-revisiting
resistant algorithms. In the paper we present a new revisiting
resistant I/O efficient LTL model checking algorithm. We analyze
its theoretical I/O complexity and we experimentally compare its
performance to already existing I/O efficient LTL model checking

Item Type:Conference or Workshop Item
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Metis ID: 251039