Comparing DLLs and Shift Registers for Low-Jitter Multi-phase Clock Generation


Share/Save/Bookmark

Gao, X. and Klumperink, E.A.M. and Nauta, B. (2007) Comparing DLLs and Shift Registers for Low-Jitter Multi-phase Clock Generation. In: ProRISC 2007, 18th Annual Workshop on Circuits, Systems and Signal Processing, 29-30 Nov 2007, Veldhoven, the Netherlands.

[img]PDF
Restricted to UT campus only
: Request a copy
218Kb
Abstract:In this paper we compare a Shift Register (SR) to a Delay Locked Loop (DLL) for Multi Phase Clock Generation (MPCG), and motivate why a SR is often better. For a given power budget, we show that a SR generates less jitter than a DLL when both are realized with Current Mode Logic (CML) circuits and white noise is assumed. This is due to differences in jitter accumulation and the possibility to choose latch delays in a SR much smaller than the delays of DLL elements. For N-phase clock generation, the SR also functions as a divide-by-N and requires a VCO with N times higher frequency than the DLL counterpart. However, this can be done in a power neutral way and can even have advantages like higher quality factor and less area for the inductors.
Item Type:Conference or Workshop Item
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/61886
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page

Metis ID: 245729