A Language and Toolset for the Synthesis and Efficient Simulation of Clock-Cycle-True Signal-Processing Algorithms


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Hofstra, Klaas L. and Gerez, Sabih H. and Kampen van, David (2005) A Language and Toolset for the Synthesis and Efficient Simulation of Clock-Cycle-True Signal-Processing Algorithms. In: ProRISC 2005, 16th Workshop on Circuits, Systems and Signal Processing, 17-18 November 2005, Veldhoven, The Netherlands.

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Abstract:Optimal simulation speed and synthesizability are contradictory requirements for a hardware description language. This paper presents a language and toolset that enables both synthesis and fast simulation of fixed-point signal processing algorithms at the register-transfer level using a single system description. This is achieved by separate code generators for different purposes. Code-generators have been developed for fast simulation (using ANSI-C) and for synthesis (using VHDL). The simulation performance of the proposed approach has been compared with other known methods and turns out to be comparable in speed to the fastest among them.
Item Type:Conference or Workshop Item
Copyright:© STW, Technology Foundation 2005
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/59554
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Metis ID: 226845