Low Power Implementation of Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures
Zhang, Qiwei and Wolkotte, Pascal and Smit, Gerard and Rivaton, Arnaud and Quevremont, Jérôme (2005) Low Power Implementation of Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures. In: ProRISC 2005, 16th Workshop on Circuits, Systems and Signal Processing, 17-18 November 2005, Veldhoven, The Netherlands (pp. pp. 465-469).
|Abstract:||The DRM standard for digital radio broadcast in the AM band requires integrated devices for radio receivers at very low power. A System on Chip (SoC) call DiMITRI was developed based on a dual ARM9 RISC core architecture. Analyses showed that most computation power is used in the Coded Orthogonal Frequency Division Multiplexing (COFDM) demodulation to compute Fast Fourier Transforms (FFT) and inverse transforms (IFFT) on complex samples. These FFTs have to be computed on non power-of-two numbers of samples, which is very uncommon in the signal processing world. The results obtained with this chip, lead to the objective to decrease the power dissipated by the COFDM demodulation part using a coarse-grain reconfigurable structure as a coprocessor. This paper introduces two different coarse-grain architectures: PACT XPP technology and the Montium, developed by the University of Twente, and presents the implementation of a
Fast Fourier Transform on 1920 complex samples. The implementation result on the Montium shows a saving of a factor 35 in terms of processing time, and 14 in terms of power consumption compared to the RISC implementation, and a
smaller area. Then, as a conclusion, the paper presents the next steps of the development and some development issues.
|Item Type:||Conference or Workshop Item|
|Copyright:||© 2005 Technology Foundation, STW|
Electrical Engineering, Mathematics and Computer Science (EEMCS)
|Link to this item:||http://purl.utwente.nl/publications/59553|
|Export this item as:||BibTeX|
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