Small-Delay Fault BIST in High-Speed Chip Interfaces


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Petre, Octvian and Kerkhoff, Hans G. (2004) Small-Delay Fault BIST in High-Speed Chip Interfaces. In: ProRISC 2004, 15th Annual Workshop on Circuits, Systems and Signal Processing, 25-26 Nov 2004, Veldhoven, the Netherlands (pp. pp. 429-434).

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Abstract:During the past years, due to the decrease of the minimum feature size in CMOS technology, the on-chip clock frequencies have increased dramatically ranging into the GHz domain. This increase has also pushed the need for higher data-transfer rates between these high-speed ICs, in order to optimize the entire PCB system. As a result, the clock/data skew can span tens of clock cycles. In order to cope with this skew, synchronization strategies have been developed which rely on either analogue or digital multitap delay-lines. In order for the synchronization mechanism to function properly, all tap-delays of the delay-line should have the same values within few percentages. This paper presents a technique, based on the oscillation method, to measure tap-delays of a delay-line with an accuracy of §10ps. A chip has also been implemented in an UMC 0.18¹m CMOS technology to prove our assumption. The measurements carried out on the chip confirmed the above mentioned accuracy.
Item Type:Conference or Workshop Item
Copyright:© STW, Technology Foundation
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Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/59502
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