A 1.35 GS/s, 10b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS


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Louwsma, Simon M. and Tuijl, Ed J.M. van and Vertregt, Maarten and Nauta, Bram (2007) A 1.35 GS/s, 10b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS. In: IEEE Symposium on VLSI Circuits, VLSI 2007, 14-16 June 2007, Kyoto, Japan (pp. pp. 62-63).

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Abstract:A time-interleaved ADC is presented with 16 channels, each consisting of two Successive Approximation (SA) ADCs in a pipeline configuration. Three techniques are presented to increase the speed of an SA-ADC. Single channel performance is 6.9 ENOB at an input frequency of 4 GHz. Multi-channel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz and a FoM of 0.6 pJ/conversion-step.
Item Type:Conference or Workshop Item
Copyright:© 2007 IEEE
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/58156
Official URL:http://dx.doi.org/10.1109/VLSIC.2007.4342766
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