A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects

Mensink, Eisse and Schinkel, Daniël and Klumperink, Eric and Tuijl van, Ed and Nauta, Bram (2007) A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects. In: IEEE International Solid-State Circuits Conference, ISSCC 2007, 11-15 February 2007, San Francisco, CA, USA.

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Abstract:	A low-swing transceiver for 10mm-long 0.54mum-wide on-chip interconnects is presented. A capacitive pre-emphasis transmitter lowers the power and increases the bandwidth. The receiver uses DFE with a power-efficient continuous-time feedback filter. The transceiver, fabricated in 1.2V 90nm CMOS, achieves 2Gb/s. It consumes 0.28pJ/b, which is 7times lower than earlier work
Item Type:	Conference or Workshop Item
Copyright:	© 2007 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/58151
Official URL:	http://dx.doi.org/10.1109/ISSCC.2007.373470
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