Low-Jitter Multi-phase Clock Generation: a Comparison between DLLs and Shift Registers

Gao, X. and Klumperink, E.A.M. and Nauta, B. (2007) Low-Jitter Multi-phase Clock Generation: a Comparison between DLLs and Shift Registers. In: IEEE International Symposium on Circuits and Systems, ISCAS 2007, 27-30 May 2007, New Orleans, LA.

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Abstract:	This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when both are realized with current mode logic (CML) circuits and white noise is assumed. This is due to the factor that the shift register MPCG has no jitter accumulation from one clock phase to the other as in the DLL based MPCG. For N-phase clock generation, the shift register MPCG needs a reference clock with N times higher frequency and thus requires a VCO with higher frequency than the DLL counterpart. However, we can show that this does not lead to additional power consumption.
Item Type:	Conference or Workshop Item
Copyright:	© 2007 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/58147
Official URL:	http://dx.doi.org/10.1109/ISCAS.2007.378767
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