High-speed global on-chip interconnects and transceivers
Mensink, Eisse (2007) High-speed global on-chip interconnects and transceivers. thesis.
|Abstract:||The data rate of global on-chip interconnects (up to 10 mm) is limited by a large distributed resistance and capacitance. This thesis describes methods to increase the achievable data rate of global on-chip interconnects with minimal chip area and power consumption, while maintaining data integrity.
The small RC bandwidth of global interconnects limits the achievable data rate. For highest bandwidth per area, all interconnect dimensions (width, spacing, height and oxide thickness) should be chosen equal and small. The bandwidth can be increased by choosing suitable termination impedances. A capacitive source impedance increases the bandwidth by a factor of three. In addition, the capacitive source impedance decreases power consumption in the interconnect. A small resistive load impedance also increases the bandwidth by a factor of three and decreases the dynamic power consumption. However, the static power consumption can still be high.
In order to maintain data integrity, a low offset sense amplifier is used to restore the low voltage swing at the output of the interconnect to full-swing. Furthermore, differential interconnects are used to be robust against supply noise, substrate noise and crosstalk from crossing interconnects. Crosstalk from neighboring interconnects that run in parallel is canceled with a single twist in every even differential interconnect and a double twist in every uneven differential interconnect. The optimal positions of the twists depend on the termination impedances.
A conventional transceiver in 0.13 μm CMOS with an inverter for both the transmitter and thereceiver, achieves 550 Mb/s/ch over a 10 mm long uninterrupted differential interconnect. Power consumption is 3.4 pJ/b at 50% data activity. An alternative transceiver in 0.13 μm CMOS, presented in this work, achieves 3 Gb/s/ch by using pulse-width pre-emphasis at the transmitter and a low-ohmic load resistance at the receiver. Power consumption is 2 pJ/b at 50% data activity. Our next improvement is a transceiver in 90m CMOS that achieves 2 Gb/s/ch by using a capacitive pre-emphasis transmitter and decision feedback equalization at the receiver. Power consumption is only 0.28 pJ/b at 50% data activity with low static power consumption.
|Link to this item:||http://purl.utwente.nl/publications/57868|
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