Back to University of Twente portal
Design-for-delay-testability techniques for high-speed digital circuits
Vermaak, Hermanus Jacobus (2005) Design-for-delay-testability techniques for high-speed digital circuits. thesis.
![[img]](http://doc.utwente.nl/style/images/fileicons/application_pdf.png)
| PDF 1323Kb |
| Abstract: | The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is
getting more and more important. |
| Item Type: | Thesis |
| Faculty: | Electrical Engineering, Mathematics and Computer Science (EEMCS) |
| Research Group: | |
| Link to this item: | http://purl.utwente.nl/publications/57440 |
| Export this item as: | BibTeX EndNote HTML Citation Reference Manager |
Show download statistics for this publication
Show download statistics for this publicationRepository Staff Only: item control page
Metis ID: 226912