Design-for-delay-testability techniques for high-speed digital circuits


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Vermaak, Hermanus Jacobus (2005) Design-for-delay-testability techniques for high-speed digital circuits. thesis.

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Abstract:The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is
getting more and more important.
Item Type:Thesis
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/57440
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Metis ID: 226912