Testability enhancement using physical design rules in a CMOS cell library

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Blom, F.C. and Oliver, J. and Rullan, M. and Ferrer, C. (1993) Testability enhancement using physical design rules in a CMOS cell library. Microprocessing and Microprogramming, 39 (2-5). pp. 245-248. ISSN 0165-6074

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Abstract:In order to achieve a good level of reliability we use a test strategy based on Layout Level Design For Testability (LLDFT) rules. These rules prevent the faults or reduce the appearance probability of them. We apply a practical set of LLDFT rules on the cells of the library designed on the Centre Nacional de Microelectrònica in order to obtain a highly testable cell library.
Item Type:Article
Copyright:© 1993 Elsevier Science
Link to this item:http://purl.utwente.nl/publications/57392
Official URL:http://dx.doi.org/10.1016/0165-6074(93)90098-6
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