A 70 MSample/s 110 mW 8 b CMOS folding interpolating A/D Converter


Nauta, B. and Venes, A.G.W. (1995) A 70 MSample/s 110 mW 8 b CMOS folding interpolating A/D Converter. In: 42nd IEEE International Solid-State Circuits Conference, ISSCC 1995, 15-17 Feb 1995, San Francisco, CA, USA (pp. pp. 276-277).

open access
Abstract:In bipolar technology the folding and interpolation technique has proven to be successful for high sample rates. This paper investigates the possibilities of this technique in CMOS. The major advantage of folding and interpolation in CMOS lies in the field of high sample rate in combination with low power consumption and small chip area. The folding converter requires little power to drive the input compared to other converters since the input behaves like a linear and constant capacitor. For similar reasons the power consumption of the reference ladder of the folding converter can be kept low. The circuit reported here runs at 70 MSample/s and dissipates only 110 mW. There are versions for 5 V and 3.3 V supplies and they are realized in a 0.8 μm CMOS process.
Item Type:Conference or Workshop Item
Copyright:© 1995 IEEE
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Link to this item:http://purl.utwente.nl/publications/57311
Official URL:https://doi.org/10.1109/ISSCC.1995.535554
Export this item as:BibTeX
HTML Citation
Reference Manager


Repository Staff Only: item control page