A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects

Schinkel, Daniël and Mensink, Eisse and Klumperink, Eric A.M. and Tuijl van, Ed (A.J.M.) and Nauta, Bram (2006) A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects. IEEE Journal of Solid-State Circuits, 41 (1). pp. 297-306. ISSN 0018-9200

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Abstract:	Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. Repeaters can partly bridge this gap, but the classical repeater insertion approach requires a large number of repeaters while the intrinsic data capacity of each interconnect-segment is only partially used. In this paper we analyze interconnects and show how a combination of layout, termination and equalization techniques can significantly increase the data rate for a given length of uninterrupted interconnect. To validate these techniques, a bus-transceiver test chip in a 0.13-/spl mu/m, 1.2-V, 6-M copper CMOS process has been designed. The chip uses 10-mm-long differential interconnects with wire widths and spacing of only 0.4 /spl mu/m. Differential interconnects are insensitive to common-mode disturbances (e.g., non-neighbor crosstalk) and enable the use of twists to mitigate neighbor-to-neighbor crosstalk. With transceivers operating in conventional mode, the chip achieves only 0.55 Gb/s/ch. The achievable data rate increases to 3 Gb/s/ch (consuming 2 pJ/bit) with a pulse-width pre-emphasis technique, used in combination with resistive termination.
Item Type:	Article
Copyright:	© 2006 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/57310
Official URL:	http://dx.doi.org/10.1109/JSSC.2005.859880
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