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A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter
Nauta, Bram and Venes, Ardie G.W. (1995) A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter. IEEE Journal of Solid-State Circuits, 30 (12). pp. 1302-1308. ISSN 0018-9200
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| Abstract: | A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm2 in 0.8 μm CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW. |
| Item Type: | Article |
| Copyright: | © 1995 IEEE |
| Link to this item: | http://purl.utwente.nl/publications/57299 |
| Official URL: | http://dx.doi.org/10.1109/4.482155 |
| Export this item as: | BibTeX EndNote HTML Citation Reference Manager |
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