Architecture Design Space Exploration for Streaming Applications Through Timing Analysis

Wiggers, Maarten H. and Kavaldjiev, Nikolay and Smit, Gerard J.M. and Jansen, Pierre G. (2005) Architecture Design Space Exploration for Streaming Applications Through Timing Analysis. [Report]

Preview

PDF
177Kb

Abstract:	In this paper we compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN $\2$ case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the application¿s throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations.
Item Type:	Report
Copyright:	© 2005 CTIT
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Computer Architecture for Embedded Systems (CAES)
Link to this item:	http://purl.utwente.nl/publications/57032
Export this item as:	BibTeX EndNote HTML Citation Reference Manager

Repository Staff Only: item control page

Metis ID: 248105