A CMOS four-quadrant analog multiplier


Bult, Klaas and Wallinga, Hans (1979) A CMOS four-quadrant analog multiplier. IEEE journal of solid-state circuits, 21 (3). pp. 430-435. ISSN 0018-9200

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Abstract:A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an output current swing of 36 percent of the supply current and a bandwidth from dc to 1 MHz. The second version has floating inputs, a linearity of 0.4 percent at an output current swing of 40 percent of the supply current and a bandwidth from dc to above 4.5 MHz.
Item Type:Article
Copyright:© 1986 IEEE
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/56126
Official URL:https://doi.org/10.1109/JSSC.1986.1052546
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