Design and implementation of a hierarchical testable architecture using the boundary scan standard

Riessen van, R.P. and Kerkhoff, H.G. and Kloppenburg, A. (1989) Design and implementation of a hierarchical testable architecture using the boundary scan standard. In: 1st European Test Conference, 1989, 12-14 April 1989, Paris, France.

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Abstract:	A standardized and structured test methodology is described which is based on the boundary-scan proposal of JTAG (Joint Test Action Group). The architecture ensures the testability of the hardware from printed-circuit-board level down to integrated-circuit level. In addition, the architecture has the feature of built-in self-test at the IC level. The implementation of the architecture by means of a self-test compiler is discussed. The test hardware for the hierarchically testable architecture at the macro level consists of test interface elements and a macro test processor; these components are examined in detail
Item Type:	Conference or Workshop Item
Copyright:	©1989 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Computer Architecture for Embedded Systems (CAES)
Link to this item:	http://purl.utwente.nl/publications/56094
Official URL:	http://dx.doi.org/10.1109/ETC.1989.36231
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