Layout level design for testability strategy applied to a CMOS cell library


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Blom, F.C. and Oliver, J. and Rullan, M. and Ferrer, C. (1993) Layout level design for testability strategy applied to a CMOS cell library. In: IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993, 27-29 October 1993 , Venice, Italy.

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Abstract:The layout level design for testability (LLDFT) rules used here allow to avoid some hard to detect faults or even undetectable faults on a cell library by modifying the cell layout without changing their behavior and achieving a good level of reliability. These rules avoid some open faults or reduce their appearance probability. The main purpose has been to apply that set of LLDFT rules on the cells of the library designed at the Centre Nacional de Microelectronica (CNM) in order to obtain a highly testable cell library. The authors summarize the main results (area overhead and performance degradation) of the application of the LLDFT rules on the cells
Item Type:Conference or Workshop Item
Copyright:©1993 IEEE
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Link to this item:http://purl.utwente.nl/publications/56054
Official URL:http://dx.doi.org/10.1109/DFTVS.1993.595782
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