Designing and implementing an architecture with boundary scan

Riessen van, R.P. and Kerkhoff, H.G. and Kloppenburg, A. (1990) Designing and implementing an architecture with boundary scan. IEEE Design & Test of Computers, 7 (1). pp. 9-19. ISSN 0740-7475

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Abstract:	A description is given of a standardized structured test methodology based on the boundary-scan proposal from the Joint Test Action Group (JTAG), which is now IEEE proposed standard P1149.1. Boundary scan does not address testability at the IC level, primarily because there is no standard for designing built-in self-testing (BIST) circuits. An architecture called the hierarchical testable, or H-testable, architecture that is compatible with the JTAG boundary-scan standard for PCB testing and provides BIST at the IC level is presented. The two have been merged, ensuring testability of the hardware from the printed-circuit-board level down to integrated-circuit level. In addition, the architecture has built-in self-test at the IC level. The authors have implemented this design using a self-test compiler
Item Type:	Article
Copyright:	©1990 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Computer Architecture for Embedded Systems (CAES)
Link to this item:	http://purl.utwente.nl/publications/55736
Official URL:	http://dx.doi.org/10.1109/54.46889
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