Experience with a clustered parallel reduction machine


Beemster, M. and Hartel, P.H. and Hertzberger, L.O. and Hofman, R.F.H. and Langendoen, K.G. and Li, L.L. and Milikowski, R. and Vree, W.G. and Barendregt, H.P. and Mulder, J.C. (1993) Experience with a clustered parallel reduction machine. Future Generation Computer Systems, 9 (3). pp. 175-200. ISSN 0167-739X

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Abstract:A clustered architecture has been designed to exploit divide and conquer parallelism in functional programs. The programming methodology developed for the machine is based on explicit annotations and program transformations. It has been successfully applied to a number of algorithms resulting in a benchmark of small and medium size parallel functional programs. Sophisticated compilation techniques are used such as strictness analysis on non-flat domains and RISC and VLIW code generation. Parallel jobs are distributed by an efficient hierarchical scheduler. A special processor for graph reduction has been designed as a basic block for the machine. A prototype of a single cluster machine has been constructed with stock hardware. This paper describes the experience with the project and its current state.
Item Type:Article
Copyright:© 1993 Elsevier Science B.V.
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/55735
Official URL:https://doi.org/10.1016/0167-739X(93)90011-D
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