Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures

Share/Save/Bookmark

Rivaton, Arnaud and Quevremont, Jérôme and Zhang, Qiwei and Wolkotte, Pascal and Smit, Gerard (2005) Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures. In: International Symposium on System-on-Chip, SoC 2005, 15-17 Nov. 2005, Tampere, Finland (pp. pp. 82-85).

open access
[img]
Preview
PDF
1MB
Abstract:To improve power figures of a dual ARM9 RISC core architecture targeting low-power digital broadcasting applications, the addition of a coarse-grain architecture is considered. This paper introduces two of these structures: PACT's XPP technology and the Montium, developed by the University of Twente, and presents the implementation of a Fast Fourier Transform on 1920 complex samples on both of them. Results in terms of processing time, resource utilization and energy dissipation are described and compared to those we have obtained on the RISC core. Then, as a conclusion, the paper presents the next steps of the development and some development issues.
Item Type:Conference or Workshop Item
Copyright:©2005 IEEE
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/54759
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page

Metis ID: 229225