Energy Model of Networks-on-Chip and a Bus

Wolkotte, Pascal T. and Smit, Gerard J.M. and Kavaldjiev, Nikolay and Becker, Jens E. and Becker, Jürgen (2005) Energy Model of Networks-on-Chip and a Bus. In: Proceedings of the International Symposium on System-on-Chip (SoC 2005). IEEE Computer Society, pp. 82-85. ISBN 9780780392946

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Abstract:	A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links
Item Type:	Book Section
Copyright:	© 2005 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Computer Architecture for Embedded Systems (CAES)
Link to this item:	http://purl.utwente.nl/publications/54547
Official URL:	http://dx.doi.org/10.1109/ISSOC.2005.1595650
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