A CSP-Based Trajectory for Designing Formally Verified Embedded Control Software


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Jovanovic, Dusko S. and Liet, Geert K. and Broenink, Jan F. (2005) A CSP-Based Trajectory for Designing Formally Verified Embedded Control Software. In: 49th Conference on Electronic, Telecommunications, Computer science, Automatics, and Nuclear technique, ETRAN 2005, June 5-10 2005, Budva, Montenegro (pp. pp. 285-288).

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Abstract:This paper presents in a nutshell a procedure for producing formally verified concurrent software. The design paradigm provides means for translating block-diagrammed models of systems from various problem domains in a graphical notation for process-oriented architectures. Briefly presented CASE tool allows code generation both for formal analysis of the models of software and code generation in a target implementation language. For formal analysis a highquality commercial formal checker is used.
Item Type:Conference or Workshop Item
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Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/53550
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