An audio FIR-DAC in a BCD process for high power Class-D amplifiers


Doorn, T.S. and Tuijl, E. van and Schinkel, D. and Annema, A.J. and Berkhout, M. and Nauta, B. (2005) An audio FIR-DAC in a BCD process for high power Class-D amplifiers. In: 31st European Solid-State Circuits Conference, ESSCIRC 2005, 12-16 September 2005, Grenoble, France (pp. pp. 459-462).

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Abstract:A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant nature of this PWM-signal. An impulse response with only positive coefficients was chosen, because of its resistance to deadzone and mismatch. With a DAC current of 0.5 mA, the dynamic range is 111 dB (A-weighted), with SINAD = 103 dB (A-weighted). The current consumption is 1mA for the analog part and 4.8 mA for the digital part. The power consumption is 29 mW at V/sub dd/ = 5 V and the chip area is 2 mm/sup 2/ including the reference diode that can be shared by more channels.
Item Type:Conference or Workshop Item
Copyright:© 2005 IEEE
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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