A 3Gb/s/ch Transceiver for RC-limited On-Chip Interconnects

Schinkel, Daniël and Mensink, Eisse and Klumperink, Eric and Tuijl van, Ed and Nauta, Bram (2005) A 3Gb/s/ch Transceiver for RC-limited On-Chip Interconnects. In: IEEE International Solid-State Circuits Conference, ISSCC 2005, February 6-10, 2005, San Francisco, USA.

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Abstract:	A bus-transceiver chip in 0.13 /spl mu/m CMOS uses 10mm uninterrupted differential interconnects of 0.8 /spl mu/m pitch (82MHz RC-limited bandwidth). The chip achieves 3Gb/s/ch using a pulse-width pre-emphasis technique in combination with resistive termination while twisted interconnects mitigate crosstalk. Power consumption is 6mW/ch at a 1.2V supply.
Item Type:	Conference or Workshop Item
Copyright:	© 2005 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/52558
Official URL:	http://dx.doi.org/10.1109/ISSCC.2005.1494031
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