A 3Gb/s/ch Transceiver for RC-limited On-Chip Interconnects


Schinkel, Daniël and Mensink, Eisse and Klumperink, Eric and Tuijl, Ed van and Nauta, Bram (2005) A 3Gb/s/ch Transceiver for RC-limited On-Chip Interconnects. In: IEEE International Solid-State Circuits Conference, ISSCC 2005, 6-10 February 2005, San Francisco, CA, USA (pp. pp. 386-387).

open access
Abstract:A bus-transceiver chip in 0.13 /spl mu/m CMOS uses 10mm uninterrupted differential interconnects of 0.8 /spl mu/m pitch (82MHz RC-limited bandwidth). The chip achieves 3Gb/s/ch using a pulse-width pre-emphasis technique in combination with resistive termination while twisted interconnects mitigate crosstalk. Power consumption is 6mW/ch at a 1.2V supply.
Item Type:Conference or Workshop Item
Copyright:© 2005 IEEE
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/52558
Official URL:https://doi.org/10.1109/ISSCC.2005.1494031
Export this item as:BibTeX
HTML Citation
Reference Manager


Repository Staff Only: item control page

Metis ID: 224170