Significance of Including Substrate Capacitance in the Full Chip Circuit Model of ICs under CDM Stress

Sowariraj, M.S.B. and Jong de, Peter C. and Salm, Cora and Smedes, Theo and Mouthaan, A.J. Ton and Kuper, Fred G. (2005) Significance of Including Substrate Capacitance in the Full Chip Circuit Model of ICs under CDM Stress. In: 43th Annual International Reliability Physics Symposium, April 17-21, 2005, San Jose, CA, USA.

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Abstract:	In CDM type of ESD, the IC is both the source and part of discharge current path. To study the CDM performance of an ICI a full-chip circuit model that includes the various static charge sources and its discharge path through the circuit as it occurs in reality is needed. Static charge sources in a CDM event are rhe various package capacitors. The CDM circuit models presented before only include the capacitors formed by the IC circuit design on the package and not that of die attachment plate on which the die is placed. This paper emphasizes the need to include this capacitance and presents a simple method of including this capacitor and its discharge path through the circuit during CDM stress.
Item Type:	Conference or Workshop Item
Copyright:	© 2005 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Semiconductor Components (SC)
Link to this item:	http://purl.utwente.nl/publications/51074
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