Full chip modelling of ICs under CDM stress


Sowariraj, Mary Sheela Bobby (2005) Full chip modelling of ICs under CDM stress. thesis.

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Abstract:In this thesis, CDM ESD stress on the Integrated Circuits (IC) and the various factors which affect the robustness of an IC design against CDM stress is investigated. One of the main reasons for CDM failure are the voltage gradients set across the circuit during CDM stress. The IC being also the source, its discharge current path is not constrained near the input and output pads as in other kinds of ESD stress.
Item Type:Thesis
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/50780
Official URL:http://doc.utwente.nl/50780/
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