Two Architectures for On-chip Virtual Channel Router


Kavaldjiev, Nikolay and Smit, Gerard J.M. and Jansen, Pierre G. (2004) Two Architectures for On-chip Virtual Channel Router. In: PROGRESS 2004 Symposium on Embedded Systems, Oct. 30, 2004, Nieuwegein, the Netherlands (pp. pp. 96-102).

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Abstract:This paper compares the implementation results of two architectures for virtual channel router. Since the router is used for building an on-chip network, its small size is critical. Together with the total design area we provide information about the distribution of this area between the main router blocks and thus give insight about the cost of each block. The comparison shows that one of the architectures results in smaller implementation area and overcomes some performance problems presented by the other architecture.
Item Type:Conference or Workshop Item
Copyright:©2004 STW Technology Foundation
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Metis ID: 221675