Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium Architecture

Heysters, Paul M. and Rauwerda, Gerard K. and Smit, Gerard J.M. (2004) Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium Architecture. In: 18th International Parallel and Distributed Processing Symposium, IPDPS 2004, April 26-30, 2004, Santa Fe, New Mexico.

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Abstract:	Summary form only given. A heterogeneous system-on-chip (SoC) architecture for mobile hand-held devices is proposed to overcome the battery bottleneck in these devices. This SoC contains processing tiles of different granularities. The Montium coarse-grain reconfigurable tile processor is presented. Also, an introduction to HiperLAN/2 baseband processing is given. The implementation of a HiperLAN/2 receiver on the Montium reconfigurable architecture is explained in detail. The hardware of this implemented receiver has been simulated and the performance figures are given. The configuration overhead for the receiver is very small, which enables dynamic reconfiguration. The required computational performance can be obtained at very low clock frequencies. The Montium coarse-grain reconfigurable architecture enables an energy and area efficient implementation of a HiperLAN/2 receiver.
Item Type:	Conference or Workshop Item
Copyright:	© 2004 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Computer Architecture for Embedded Systems (CAES)
Link to this item:	http://purl.utwente.nl/publications/48852
Official URL:	http://dx.doi.org/10.1109/IPDPS.2004.1303131
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