A 1.6 GS/s, 16 Times Interleaved Track & Hold with 7.6 ENOB in 0.12 µm CMOS

Louwsma, Simon M. and Tuijl van, Ed J.M. and Vertregt, Maarten and Scholtens, Peter C.S. and Nauta, Bram (2004) A 1.6 GS/s, 16 Times Interleaved Track & Hold with 7.6 ENOB in 0.12 µm CMOS. In: 30th European Solid-State Circuits Conference, ESSCIRC 2004, September 21-23, 2004, Leuven, Belgium.

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Abstract:	A 1.6 GS/s track and hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is better than 2 ps and aperture uncertainty is less than 0.8 ps (RMS). The chip includes two analog to digital converters and a switching matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm/sup 2/, excluding the AD converters. The chip is made in a 0.12 µm, 1.2 V CMOS process. Power consumption of the interleaving T/H circuit is 32 mW.
Item Type:	Conference or Workshop Item
Copyright:	© 2004 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/48365
Official URL:	http://dx.doi.org/10.1109/ESSCIR.2004.1356688
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