Test-access planning and test scheduling for embedded core-based system chips


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Goel, Sandeep Kumar (2005) Test-access planning and test scheduling for embedded core-based system chips. thesis.

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Abstract:This thesis describes parts of the research work that has been carries out at Philips Research Laboratories, Eindhoven, related to the development of TR-ARCHITECT. TR-ARCHITECT uses a five step heuristic algorithm to design a test architecture. TR-ARCHITECT designs and optimized test architectures with respect to the required ATE vector memory dept and test-application time. TR-ARCHITECT optimizes wrapper and TAM design in conjunction.
Item Type:Thesis
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/48260
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