ADC Clock Jitter Requirements for Software Radio Receivers

Arkesteijn, Vincent J. and Klumperink, Eric A.M. and Nauta, Bram (2004) ADC Clock Jitter Requirements for Software Radio Receivers. In: IEEE 60th Vehicular Technology Conference 2004 (VTC2004-Fall), 26-29 September 2004, Los Angeles, California, USA.

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Abstract:	The effective number of bits of an analogue-to-digital converter (ADC) is limited not only by the quantisation step inaccuracy, but also by sampling time uncertainty. According to a commonly used model, timing jitter errors should not introduce a sampling error bigger than 1 quantisation level for full swing input signals at a frequency equal to half the sample rate. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. The paper explores the clock jitter requirements for a software radio application, using a more realistic model found in the literature and taking into account both the power spectrum of the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter is not the limiting factor in the feasibility of software radio receivers.
Item Type:	Conference or Workshop Item
Copyright:	© 2004 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/48126
Official URL:	http://dx.doi.org/10.1109/VETECF.2004.1400385
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