Designing outside rail constraints

Share/Save/Bookmark

Annema, Anne-Johan and Nauta, Bram and Langevelde, Ronald van and Tuinhout, Hans (2004) Designing outside rail constraints. In: IEEE International Solid-State Circuits Conference, ISSCC 2004, 15-19 February 2004, San Francisco, CA, USA (pp. pp. 134-135).

open access
[img]
Preview
PDF
496kB
Abstract:CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds matching tolerances requiring active cancellation techniques. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin and thick-oxide transistors.
Item Type:Conference or Workshop Item
Copyright:© 2004 IEEE
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/47894
Official URL:http://dx.doi.org/10.1109/ISSCC.2004.1332630
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page

Metis ID: 218888