A 2.5 10 10 GHz Clock Multiplier Unit with 0.22ps RMS Jitter in a 0.18/spl mu/m CMOS Technology

Beek van de, Remco C.H and Vaucher, Cicero S. and Leenaerts, Dominicus M.W. and Pavlovic, Nenad and Mistry, Ketan and Klumperink, Eric A.M. and Nauta, Bram (2003) A 2.5 10 10 GHz Clock Multiplier Unit with 0.22ps RMS Jitter in a 0.18/spl mu/m CMOS Technology. In: IEEE International Solid-State Circuits Conference, ISSCC 2003, 9-13 February 2003, San Francisco, CA, USA.

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Abstract:	A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at 2.5GHz. The jitter and power dissipation are lower than that of previous CMOS implementations.
Item Type:	Conference or Workshop Item
Copyright:	© 2003 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/45864
Official URL:	http://dx.doi.org/10.1109/ISSCC.2003.1234256
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