Analysis of Random Jitter in a Clock Multiplying DLL Architecture


Share/Save/Bookmark

Beek van de, R.C.H and Klumperink, E.A.M. and Vaucher, C.S. and Nauta, B. (2001) Analysis of Random Jitter in a Clock Multiplying DLL Architecture. In: ProRISC 2001, 12th Annual Workshop on Circuits, Systems and Signal Processing, 29-30 November 2001, Veldhoven, the Netherlands.

[img]PDF
605Kb
Abstract:In this paper, a thorough analysis of the jitter behavior of a Delay Locked Loop (DLL) based clock multiplying architecture is presented. The noise sources that are included in the analysis are the noise of the delay elements, the reference jitter and the noise of the Phase Frequency Detector and Charge Pump combination. It is shown that the effect of all noise sources on the output timing jitter can be minimized by minimizing the loop gain of the DLL. This means that the loop is merely used to tune the delay of the Delay Line to a nominal value of exactly one reference input period; the loop is ineffective in filtering jitter. The analysis results are verified using high-level simulations, with good agreement.
Item Type:Conference or Workshop Item
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/42541
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page

Metis ID: 201862