Novel Technique for Reliability Testing of Silicon Integrated Circuits


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Le Minh, P. and Wallinga, H. and Woerlee, P.H. and Berg van den, A. and Holleman, J. (2001) Novel Technique for Reliability Testing of Silicon Integrated Circuits. In: In-line characterization, yield, reliability, and failure analysis in microelectronic manufacturing II, 31 May - 1 June 2001, Edinburgh, UK.

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Item Type:Conference or Workshop Item
Copyright:© 2001 SPIE
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Electrical Engineering, Mathematics and Computer Science (EEMCS)
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Link to this item:http://purl.utwente.nl/publications/42082
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Metis ID: 200336