Max-Log-MAP Mapping on an FPFA


Heysters, Paul M. and Smit, Lodewijk T. and Smit, Gerard J.M. and Havinga, Paul J.M. (2002) Max-Log-MAP Mapping on an FPFA. In: International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2002, June 24-27, 2002, Las Vegas, Nevada (pp. pp. 90-96).

open access
Abstract:Computational-intensive parts of algorithms often execute energy-inefficient on general-purpose processors. Reconfigurable hardware could improve the energy efficiency while maintaining a sufficient level of flexibility. In a case study, the computational-intensive Max-log-MAP algorithm of Turbo decoding is mapped on the Field Programmable Function Array (FPFA). The FPFA is an architecture for a dynamically reconfigurable device that consists of a matrix of reconfigurable processor tiles.
Item Type:Conference or Workshop Item
Copyright:© 2002 CSREA Press
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:
Export this item as:BibTeX
HTML Citation
Reference Manager


Repository Staff Only: item control page

Metis ID: 210499