Max-Log-MAP Mapping on an FPFA

Heysters, Paul M. and Smit, Lodewijk T. and Smit, Gerard J.M. and Havinga, Paul J.M. (2002) Max-Log-MAP Mapping on an FPFA. In: International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2002, June 24-27, 2002, Las Vegas, Nevada.

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Abstract:	Computational-intensive parts of algorithms often execute energy-inefficient on general-purpose processors. Reconfigurable hardware could improve the energy efficiency while maintaining a sufficient level of flexibility. In a case study, the computational-intensive Max-log-MAP algorithm of Turbo decoding is mapped on the Field Programmable Function Array (FPFA). The FPFA is an architecture for a dynamically reconfigurable device that consists of a matrix of reconfigurable processor tiles.
Item Type:	Conference or Workshop Item
Copyright:	© 2002 CSREA Press
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Computer Architecture for Embedded Systems (CAES) Pervasive Systems (PS)
Link to this item:	http://purl.utwente.nl/publications/38403
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