Channel Communication and Reconfigurable Hardware


Share/Save/Bookmark

Bos, Martinus and Havinga, Paul J.M. and Smit, Gerard J.M. (2000) Channel Communication and Reconfigurable Hardware. In: Progress 2000 Workshop on Embedded Systems, October 13, 2000, Utrecht, The Netherlands (pp. pp. 17-21).

open access
[img]
Preview
PDF
16kB
Abstract:Many applications can be structured as a set of processes or threads that communicate via channels. These threads can be executed on various platforms (e.g. general purpose CPU, DSP, FPGA, etc). In our research we apply channels as a basic communication mechanism between threads in a reconfigurable system. The research involves providing system level functions to describe the setup of communicating threads, which may now either run timeshared on a general CPU or in dynamically-setup special purpose logic that runs on reconfigurable hardware. The use of channels and threads running in both software and hardware, will be made transparent for the application level programmers by the system level functions. By first describing the threads and how they are connected and then letting the operating system decide on 'geographical' placement of the threads and buffers, multiprogramming will be supported and programs will be able to run on different setups of hardware (i.e. different amount of CPUs or available programmable logic). This is an ongoing work, the paper is a collection of thoughts, which lead to a first setup of rudimentary support functions in the operating system.
Item Type:Conference or Workshop Item
Copyright:© STW Technology Foundation
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/19152
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page

Metis ID: 119675