Processen with 'incomplete' sensitivity lists and their synthesis aspects

Molenkamp, Egbert and Mekenkamp, Gerhard E. (1997) Processen with 'incomplete' sensitivity lists and their synthesis aspects. In: VHDL International Users' Forum, 1997, October 19-22, 1997, Arlington, VA, USA.

Preview

PDF
448Kb

Abstract:	Synthesis tools only support a subset of VHDL. In this paper, we focus on the synthesis aspects of processes with an incomplete sensitivity list. In general, processes with a sensitivity list are used to describe combinational logic and clocked logic. The sensitivity list is called `complete' when all signals which are read from within that process are in the sensitivity list, otherwise it has an `incomplete' sensitivity list. Most, if not all, synthesis tools require that the processes used to describe combinational logic should have a `complete' sensitivity list, while for synchronous logic only the reset, if any, and clock signals should be in the sensitivity list. Beside these two applications of processes with sensitivity lists, there is a vague support for other incomplete sensitivity lists, sometimes resulting in latches in the circuit and sometimes resulting in logic that does not have the proper behaviour. This paper focuses on the synthesis aspects of processes with an incomplete sensitivity list, and presents a method to synthesise a subset of these processes. Also, the problem of synthesising processes with an incomplete sensitivity list is discussed
Item Type:	Conference or Workshop Item
Copyright:	©1997 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Computer Architecture for Embedded Systems (CAES)
Link to this item:	http://purl.utwente.nl/publications/18993
Official URL:	http://dx.doi.org/10.1109/VIUF.1997.623933
Export this item as:	BibTeX EndNote HTML Citation Reference Manager

Show download statistics for this publication

Repository Staff Only: item control page

Metis ID: 119515