Mapping the SISO module of the Turbo decoder to a FPFA


Share/Save/Bookmark

Smit, Gerard J.M. and Heysters, Paul M. and Havinga, Paul J.M. and Smit, Lodewijk T. and Dilessen, John and Huisken, Jos (2000) Mapping the SISO module of the Turbo decoder to a FPFA. In: Second International Symposium on Mobile Multimedia Systems & Applications, MMSA 2000, 9-10 November 2000, Delft, The Netherlands.

[img]
Preview
PDF
133Kb
Abstract:In the CHAMELEON project a reconfigurable systems-architecture, the Field Programmable Function Array (FPFA) is introduced. FPFAs are reminiscent to FPGAs, but have a matrix of ALUs and lookup tables instead of Configurable Logic Blocks (CLBs). The FPFA can be regarded as a low power reconfigurable accelerator for an application specific domain. In this paper we show how the SISO (Soft Input Soft Output) module of the Turbo decoding algorithm can be mapped on the reconfigurable FPFA.
Item Type:Conference or Workshop Item
Copyright:© 2000 TU Delft, UbiCom, Ubiquitous Communications
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/17301
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page

Metis ID: 114196