Transmission Line Model Testing of Top-Gate Amorphous Silicon Thin Film Transistors


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Tosic, N. and Kuper, F.G. and Mouthaan, A.J. (2000) Transmission Line Model Testing of Top-Gate Amorphous Silicon Thin Film Transistors. In: 38th Annual IEEE International Reliability Physics Symposium, 10-13 April 2000, San Jose, CA.

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Abstract:In this paper, for the first time Transmission Line Model (TLM) characterization is used to analyze ESD events in amorphous silicon thin film transistors (¿-Si:H TFT). It will be shown that, above an ESD degradation threshold voltage, deterioration of electrical characteristics sets in, and that above another ESD failure threshold voltage, dielectric breakdown occurs. Electrical simulations of an ¿-Si:H TFT confirm creation of positive interface charges as being the most likely cause of the deterioration process. Two failure modes have been identified by failure analysis
Item Type:Conference or Workshop Item
Copyright:©2000 IEEE
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/17064
Official URL:http://dx.doi.org/10.1109/RELPHY.2000.843929
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Metis ID: 113950