A CMOS four-quadrant analog current multiplier

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Wiegerink, Remco J. (1991) A CMOS four-quadrant analog current multiplier. In: IEEE International Symposium on Circuits and Systems, ISCAS 1991, 11-14 June 1991, Singapore (pp. pp. 2244-2247).

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Abstract:A CMOS four-quadrant analog current multiplier is described. The circuit is based on the square-law characteristic of an MOS transistor and is insensitive to temperature and process variations. The circuit is insensitive to the body effect so it is not necessary to place transistors in individual wells. The multiplier has a large -3-dB bandwidth (50 MHz with 10-¿m transistors) and an approximately constant input impedance. The circuit was realized on a CMOS semicustom array. Measurements have shown that the nonlinearity is less than 1% at the maximum input current range and less than 0.2% when the input range is restricted to 50% of the maximum
Item Type:Conference or Workshop Item
Copyright:©1991 IEEE
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/17056
Official URL:http://dx.doi.org/10.1109/ISCAS.1991.176826
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Metis ID: 113941