A low-speed BIST framework for high-performance circuit testing


Share/Save/Bookmark

Speek, H. and Kerkhoff, H.G. and Shashaani, M. and Sachdev, M. (2000) A low-speed BIST framework for high-performance circuit testing. In: 18th IEEE VLSI Test Symposium, 2000, 30 April-4 May 2000, Montreal, Canada (pp. pp. 349-355).

open access
[img]
Preview
PDF
140kB
Abstract:Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addressed
Item Type:Conference or Workshop Item
Copyright:©2000 IEEE
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/16138
Official URL:http://dx.doi.org/10.1109/VTEST.2000.843865
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page

Metis ID: 113023