Bridging the Testing Speed Gap: Design for Delay Testability


Speek, H. and Kerkhoff, H.G. and Sachdev, M. and Shashaani, M. (2000) Bridging the Testing Speed Gap: Design for Delay Testability. In: IEEE European Test Workshop, 2000, 23-26 May 2000, Cascais, Portugal (pp. pp. 3-8).

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Abstract:The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a design for delay testability technique such that high-speed ICs can be tested using inexpensive, low-speed ATE. Also extensions for possible full BIST of delay faults are addressed
Item Type:Conference or Workshop Item
Copyright:©2000 IEEE
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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